1. Field of the Invention
The present invention relates to a clock generation circuit and an integrated circuit.
2. Description of the Related Art
In Japanese Patent Laid-Open No. 2002-108492, a two-phase clock signal-generating device 1 for generating a two-phase clock signal (an A phase clock signal, a B phase clock signal) used in a circuit device such as an ECU of a car is described as shown in FIG. 2 of Japanese Patent Laid-Open No. 2002-108492. In the two-phase clock signal-generating device 1, a CPU 3 reads sensor signals from a temperature sensor 6 and a voltage sensor 7, and determines data for setting a delay time d according to the temperature and voltage at that point in time based on a data table stored in a memory 5. A two-phase clock signal generating unit 4 receives, from the CPU 3, the data for setting the delay time d determined by the CPU 3. In the delay control units 12a and 12b of the two-phase clock signal generating unit 4, as shown in FIG. 1 (b) of Japanese Patent Laid-Open No. 2002-108492, a decoder 16 decodes the setting data and outputs a closing control signal to any one of switches 15. Accordingly, in the delay control units 12a and 12b, the number of stages of a delay buffer 14 into which an input signal passes is determined. In the two-phase clock signal generating unit 4, as shown in FIG. 1 (a) of Japanese Patent Laid-Open No. 2002-108492, the delay time d is added to an A phase clock signal by the delay control unit 12a, and the resultant signal is input into the input terminal of an OR gate 9. Further, the delay time d is added to a B phase clock signal by the delay control unit 12b, and the resultant signal is input into the input terminal of an OR gate 10. This delay time d provides a non-overlap period in which both the A phase clock signal and the B phase clock signal are at a low level as shown in FIG. 3 of Japanese Patent Laid-Open No. 2002-108492.
In this way, according to Japanese Patent Laid-Open No. 2002-108492, even in a case in which the temperature/voltage changes, which is the operational environment of a circuit device such as an ECU of a car, it is thought that the non-overlap period of the two-phase clock signal used in the circuit device can be adjusted so as to be constant.
As described above, there are many cases in which a non-overlap period of a two-phase clock is designed so as to be adjusted using a delay element with propagation delay characteristics of a logical gate such as an inverter circuit, or with propagation delay characteristics of a capacitance load or the like. Among these, the propagation delay characteristics of the logical gate will change according to changes in element characteristics due to the power supply voltage, temperature fluctuation, or variations in the manufacturing process. If a two-phase clock is generated using such a delay element, the non-overlap period of the two-phase clock will vary.
Here, considering the case in which an AD converter configured from a switched capacitor is operated using a two-phase clock, a non-overlap period is a period in which an amplifier circuit does not perform either a sampling operation or a holding operation. Consequently, in particular, in a high-speed AD converter and the like, if a non-overlap period is designed to be as short as possible, it is possible to secure a longer time for a sampling operation and a longer time for a holding operation, which is advantageous.
However, if the non-overlap period of a two-phase clock varies, when shortening the non-overlap period, the circuit may malfunction due to skew between the clocks, which could not be expected when designing the circuit, and so on. Accordingly, this sets a limit when shortening the non-overlap period.
With the technique disclosed in Japanese Patent Laid-Open No. 2002-108492, in the case in which the non-overlap time of a two-phase clock varies because of variations in element characteristics due to the manufacturing process, it may be impossible to adjust the non-overlap period of a two-phase clock signal so as to be constant.